In large CMOS logic structures, the primary source of power dissipation and noise results from the transition of logic levels throughout the structure. This power dissipation and noise can be a significant limiting factor in the implementation of large CMOS logic structures. It is noted that in CMOS circuitry, power dissipation is directly proportional to the number of bit transitions propagating through the structure.
What is needed is a way to reduce the number of logic transitions that occur in a pipelined structure while preserving the information in the data.